Single Event Latchup over-current seen for half A of Daughterboard 5... | Download Scientific Diagram
Modeling and Analysis of Single Event Effects (SEE) - SemiWiki
Integrated Single Event Latchup protection for ASICs used in space applications | Semantic Scholar
SEECA - Section 4
What are random Destructive Single Event Effects (DSEE)? | TI.com Video
Compact Modeling of Single Event Latchup of integrated CMOS circuit
Latch-up - Wikipedia
Single Event Latchup Protection Circuits | doEEEt.com
Elimination of Single Event Latchup in 90nm SRAM Technologies | Semantic Scholar
A Single Event Latch-up protection method for SRAM FPGA | Semantic Scholar
5: Single Event Latch-up principle. | Download Scientific Diagram
EngineerZone
Single Event Effects (SEEs) with High Speed ADCs: Single Event Latch-up (SEL) - Planet Analog
Figure 1 from Single-Event Latchup Modeling Based on Coupled Physical and Electrical Transient Simulations in CMOS Technology | Semantic Scholar
Single Event Effects in High Altitude Aerospace Sensor Applications - Mobility Engineering Technology
Single event and TREE latchup mitigation for a star tracker sensor: An innovative approach to system level latchup mitigation - UNT Digital Library
The Effects of Scaling and Well and Substrate Contact Placement on Single Event Latchup in Bulk CMOS Technology
![Single Event Latch-up (sel) Mitigation Detect And Mitigation Maillard; Pierre ; et al. [Xilinx, Inc.]](https://uspto.report/patent/app/20200091713/US20200091713A1-20200319-D00000.png "Single Event Latch-up (sel) Mitigation Detect And Mitigation Maillard; Pierre ; et al. [Xilinx, Inc.]")
Single Event Latch-up (sel) Mitigation Detect And Mitigation Maillard; Pierre ; et al. [Xilinx, Inc.]
QUALITATIVE CHARACTERIZATION OF SINGLE-EVENT TRANSIENT AND LATCHUP TRENDS IN 180 nm CMOS TECHNOLOGY By Cody Adam Dinkins Thesis
Space Radiation Effects on Electronics - Single Event Effects | Space Talos LTD
Single Event Effects (SEE) | Microsemi
![PDF] Single event latchup: Hardening strategies, triggering mechanisms, and testing considerations | Semantic Scholar](https://d3i71xaburhd42.cloudfront.net/74a351bb606b40d5caa2ad38e5999bbb246d974f/11-Figure1-1.png "PDF] Single event latchup: Hardening strategies, triggering mechanisms, and testing considerations | Semantic Scholar")
PDF] Single event latchup: Hardening strategies, triggering mechanisms, and testing considerations | Semantic Scholar
Comparative research on “high currents” induced by single event latch-up and transient-induced latch-up<xref ref-type="fn" rid="cpb142021fn1">*</xref>
Earlier Is Better In Latch-Up Detection
An investigation of FinFET single-event latch-up characteristic and mitigation method - ScienceDirect
SEE Single Event Effects
